(J. Trujillo, K. Liu, J. Heritage, C.E. Hung, UC Davis)

Research on field emission cathodes has been in progress at UC Davis for several years now. The thrust of this research has been in developing cathodes for use in flat panel display and microwave application, with the primary objective for this stage of the research being the formation of stable, reproducible gated cathodes. The following presents some potential applications in microwave technology, a description of a field emission cathode, the fabrication method used, and some experimental results.

Field emission arrays show promise in rf and microwave applications because they offer the potential to provide high efficiency electron guns. This efficiency is due mainly to the ability to fabricate submicron structures and small spacing between them. Tip radii of less than 1nm have been reported which provide strong field enhancement; the gate can be situated very close to the tip resulting in lower turn-on voltage and higher transconductance. Currents as high as 1mA/tip with drive voltages of less than 50V have been reported. Also, tips can be densely packed to give larger current densities. Since a density of 6 million tips/cm2 or more can be fabricated, it follows that under ideal conditions a current density as high as 6A/cm2 may be achieved.

Furthermore, electrons emitted from field emitters can be prebunched. One possible method of prebunching is done by exciting the field emitters with high power optical pulses to emit short bunches of electrons. This results in a significant reduction in the size of microwave tubes.

The Gated Silicon Field Emission Cathode

The gated field emission cathode, shown in the schematic below in Figure 1, consists of a sharp emitter tip which is either etched from or deposited onto a substrate. This tip forms the cathode. A second electrode, the gate, or "extraction grid" is placed in the proximity of the tip. The gate is supported by an insulator which provides both electrical isolation of the grid as well as a spacer, insuring the correct gate to tip spacing. During operation a potential is placed between the cathode and the extraction grid. The electric field created at the tip by this potential is magnified due to the extreme sharpness of the tip, causing electrons to be emitted. In many cases potentials as low as 15 V are sufficient to produce electron emission. In the simple diagram below, emitted electrons are collected at an anode. In reality this anode can range from a simple metallic anode or phosphor screen to complex electron optics.

Figure 1: Schematic of gated field emission cathode

Cathode Fabrication Method

Cathodes for this research are fabricated in silicon using a "Lift-off" technique. In this process, the emitter tip is formed by etching the silicon a 1 Ám disk of silicon dioxide. The silicon is etched using either wet chemistry or plasma etching. The etch is stopped just before the disk is removed as shown in Figure 2a below. The SiO2 disk that remains on top of the tip is used as a mask for aligning the gate to the tip.

The tip etch is followed by thermal oxidation step. This converts the surface layer of the silicon tip to SiO2, as shown in Figure 2b, providing two important results. First, since SiO2 can be etched with chemicals that do not affect silicon, this SiO2 layer provides a means of removing the cap once it has served its purpose. The second effect is that the silicon underneath is sharpened to an atomically sharp point. This sharp point is the key to low voltage operation.

Next, the insulation and gate layers are deposited, Figure 2c. Finally the SiO2 layer over the tip and the masking disk are removed. The final structure is shown in Figure 2d. Figure 3 is an SEM of a gated field emission cathode made using this method. This technique may be used to fabricate single tips or, more importantly for microwave applications, to form large, closely spaced array which can provide high current densities.

Figure 2. Gated silicon emitter fabrication: a) Tip etched, mask left on. b) Tip sharpened. c) Insulation andgate layers deposited. d) Tip mask lifted off.

Figure 3. A SEM photo of a gated silicon field emitter.

In addition to ATRI, this work is being supported by Hewlett Packard, Sandia National Laboratory. Funding in the past has been provided by Lawrence Livermore National Laboratory.

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